The cascode logic family is derived from the well known Emitter Coupled Logic (ECL) family, which is characterized by a systematic usage of non-saturated transistors, which, in turn, results in very high speed performances.
Given the obvious power of the Emitter Coupled Logic technology, the cascode logic technology is the ideal VLSI candidate for being implemented in high end computers. It has potentially superior power-performance attributes compared to other logic circuit technologies. Further, this technology may be integrated in low cost bipolar chips compatible with a CMOS environment. However, it also has some drawbacks which have prevented it from becoming a generalized logic technology to date.
Two-level single-ended cascode (2L-SE) circuits are well-known in the art. These two levels are generally called bottom stage and top stage levels because of the DC voltages that the signals must respect. There are two types of 2L-SE cascode circuits depending on either collector output usage or systematic emitter follower usage. These two types of 2L-SE cascode circuits are depicted respectively in FIGS. 1 and 2.
A conventional 2L-SE cascode circuit with NPN transistors and collector output usage is shown in FIG. 1. Basically, the circuit 10 of FIG. 1 is made of two sets of current switches 11 and 12 mounted in cascode and of one translator stage per output, respectively referenced 13 for the true output and 14 for the complement output. Circuit 10 is biased between a first supply voltage, a positive voltage VPP, and a second supply voltage, the ground GND.
The first set 11 of current switches is comprised of input transistors TXll and TX12, connected in a differential amplifier configuration with reference transistor TX13. Combination of current switch 11 and transistor TX13 forms the so called "bottom stage" 16. The base of transistor TX 13 is connected to a fixed reference voltage VR11 delivered by a reference voltage generator. The bottom logic input signals, All and A12, are applied to the bases of transistors TXll and TX12, respectively. The bottom stage is supplied by a constant current IO, determined by a conventional current source comprised of transistor TY11, the base of which is connected to a fixed reference voltage VRR delivered by a reference voltage generator, and resistor RE1. Said constant current IO=((VRR VBE(TY11))/REl) has to flow either through TX11,TX12 or TX13; it flows through the transistor which receives the highest base voltage. Since in this example, collectors of TXll and TX12 are tied together, the collector voltage may go low as soon as the current flows through TX11 or TX12, thus realizing a 2 Way OR function. Note that the extension to an N Way OR is trivial.
The second set 12 of current switches is comprised of input transistors TX14 and TX15 connected to a differential amplifier configuration with transistor TX16. The combination of current switch 12 and transistor TX16 forms the so called "top stage" 17. The base of transistor TX16 is connected to a fixed reference voltage VR12 delivered by a reference voltage generator. The top logic input signals N11 and N12 are applied to the bases of transistors TX14 and TX15, respectively. The constant current is determined by the same current source as for the first set of current switches. It still flows through the transistor which receives the highest base voltage. Since in this example, TX14 and TX15 collectors are tied together, the collector voltage may be low as soon as the current flows through TX14 and TX15, realizing a 2 Way 0R function. Note that the extension to an N Way OR is trivial.
Current switches 11 and 12 are loaded with a conventional resistor RCC1 mounted in parallel with a Schottky Barrier Diode (SBD) referenced SBD11. These devices are necessary to compensate variations of reference voltage VRR, which could be detrimental to the operation of the circuit at a low output logical level. Collectors of transistors TX13 and TX16 are dotted at node 18 and loaded with resistor RCT1 mounted in parallel with diode SBD12.
Bottom stage 16 and top stage 17, the loads (RCC1, SBD11, RCT1 and SBD12), and the associated current source circuitry (TY11 and RE1), form the tree 15, biased between VPP and GND. The true output T11 of the tree is available at node 18 formed by dotting collectors of transistors TX13 and TX16. The complement output C11 is available at the node where collectors of TX14 and TX15 are tied together.
Each one of the true and complement outputs receives a level translator or output stage respectively referenced 13 and 14. Level translator stage 14 for the true output is constituted with transistor TY12 mounted as an emitter follower and a current source comprised of TY13 and resistor RST1. The top output T11 is available at collector of TX16 while the bottom output T12 is available on the emitter of TY12. Similarly, level translator stage 14 for complement output is comprised of devices TY14, TY15 and TSC1. The top output C11 is available at the collector of TX14 while the bottom output C12 is available on the emitter of TY14. Either translator stage 13 or 14 also acts as a buffer for `bottom` connections.
In summary, circuit 10 may be broadly understood as being comprised of two stacking levels, the first including TX11, TX12 and TX13 forming the bottom stage and the second including TX14, TX15 and TX16 forming the top stage. Only the bottom stage is provided with a buffer stage.
The constant current source IO sets the power that the logic tree 15 will consume in performing its designed logical function. Logical operations are accomplished by selectively steering the tree current through various paths within the tree to one of two binary output summation points. Current steering is accomplished by applying logic input signals to each input of transistors in the tree, selecting the transistors that will allow the current to pass. Both sets of current switches in this example are connected so that, to get a low voltage at RCC1 resistance node, and thus a high voltage corresponding to a logical "1" at RCT1 resistance node, the current has to flow through TX14 or TX15 AND through TX11 OR TX12. The logic function is therefore an AND of the two ORs. The logical Boolean function Y1 available at output T11 is Y1=(A11+A12) (N11+N12). The complementary function Y1 is available at output C11.
Other functions like extended ORs, exclusive ORs, etc. may also be obtained by changing the connections from the first to the second set of current switches.
An important drawback of circuit 10 results from its excessive sensitivity to the capacitive loading at the top output. For example, line and wiring capacitance C1a at top output T11, has a significant impact in terms of delay (time constant), which, in turn, limits the switching speed of the cascode circuit. Therefore, this sensitivity is a serious detractor in terms of circuit performance. Circuit 10 is also sensitive to dotting in terms of delay, as any dotting will bring additional capacitances.
An improved alternative to the circuit of FIG. 1 is shown in FIG. 2 where similar devices bear corresponding references. Circuit 20 differs from circuit 10 only in the configuration of level translator stages 23 and 24. Unlike in circuit 10, the top output T21 of translator stage 23 is translated downward a VBE, through translator TY22 connected in an emitter follower configuration. As a result of this downshift, circuit 20 benefits from the buffering effect offered by transistor TY22. The bottom output T22 is translated even more by means of an output level shifter: either a PN junction (a transistor operating as a diode) or a Schottky junction. To avoid bottom stage transistor saturation in the tree, a minimum shift of 0.4 V is needed. The Schottky Barrier Diode offers a shift of 0.55 V which is convenient. On the other hand, the PN diode offers a shift of about 0.8 V which is also appropriate, but does have the inconvenience of requiring a higher VPP supply for correct functional operation.
The circuit has a much better performance-power product than the circuit of FIG. 1. The tree current is lower, as the tree performs only the logic function without any load at the tree output. In addition, TY22 and its associated current source TY23 take care of the load (wiring capacitance C2a and fan-out) at top output T21.
However, the cascode circuit 20 of FIG. 2 still presents various inconveniences, mainly caused by the presence of the output level shifters such as the SBDs.
First of all, it needs two outputs per phase out, e.g. T21 and T22 for translator stage 23. Because the second output T22 is shifted down from the emitter output, through SBD23, this shift causes circuit 20 to be non-functional below VPP=3.2 V (worst case voltage to be applied at the circuit itself after off-chip and on-chip supply voltage drops and tolerance).
As a first consequence, circuit 20 is not usable with the 3.3.+-.0.3 V VPP supply as defined by the JEDEC specifications for future CMOS products and CMOS/bipolar interfaces in the worst case conditions, where the supply voltage VPP is as low as 3 V.
As a second consequence, the top output, (e.g. T21) may be connected only to corresponding top input signals e.g. N21, N22,. . .) but not to the bottom input signals (e.g. A21, A22,. . .), of a following similar circuit, since transistors like TX21, TX22, and TX23, would saturate. Conversely, bottom output, e.g. T22, may be connected only to corresponding bottom input signals e.g. A21, A22, etc. . ., but not to the top input signals e.g. N21, N22, etc..., of a following similar circuit.
In addition, the implementation of FIG. 2 which includes two outputs per phase out, not only requires more wiring which in turn, results in lower density, but also implies two load capacitances, e.g. C2a and C2b, which are almost in parallel, because they are connected through said output level shifter which consists of a continuously conducting diode, e.g. SBD23, when the two outputs are simultaneously used.
The circuit of FIG. 2 must also use Schottky Barrier Diodes, referenced as SBD21 and SBD22, as clamping devices across collector resistors respectively referenced RCC2 and RCT2. The intent is to provide both a good definition of the voltage swing which cannot be minimized and to avoid saturation of the top output transistors such as TX24 and TX25; this may occur if the current source has wide variations due to process, temperature and power supply tolerances. In addition, said clamping devices add to the collector parasitic capacitance. As a result, the presence of these clamping devices significantly impedes the speed of the cascode circuit.
Further, a library of logic circuits based on the circuit shown in FIG. 2 would have two major inconveniences. First, it would have potentially a low power from a logical implementation point of view. The circuit of FIG. 2 provides an OR-AND function; if more complex functions are needed, appropriate standard logic circuitry has to be added, at the cost of significantly lowering integration density. Secondly, the circuit shown in FIG. 2 exhibits a limited number of logical circuits, in that it does not allow generalization to 2N-level single-ended cascode logic circuits, unless the power supply value is significantly increased, which is not the trend in designing future VLSI circuits. The primary objective of the present invention is therefore to provide a family of cascode current switch logic circuits forming a library of various logic functions which do not have the above mentioned drawbacks inherent in the conventional cascode circuits with output level shifter.